1. Field of the Invention
The present invention is generally related to test circuitry, and, more particularly, to a system and method for testing memory arrays in circuitry.
2. Discussion of the Related Art
Integrated circuits (ICs) are electrical circuits comprising transistors, resistors, capacitors, and other components on a single semiconductor “chip” on which the components are interconnected to perform a variety of functions. Typical examples of ICs include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable read only memory (EEPROM) devices) random access memory (RAM) devices, operational amplifiers and voltage regulators. A circuit designer typically designs the IC by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer-aided design (E-CAD) tools. As will be appreciated, electronic devices include analog, digital, mixed hardware, optical, electromechanical, and a variety of other electrical devices. The design and subsequent simulation of any circuit, very large scale integration (VLSI) chip, or other electrical device via E-CAD tools allows a circuit to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools utilize an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device that includes the circuit. As will be appreciated by those skilled in the art of hardware device design, a “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit “modules,” which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is the schematic of the circuit device.
In contrast, a hierarchical netlist maintains only one copy of a circuit module, which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist shows the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules are represented by “black boxes.” As will be appreciated by those skilled in the art, a “black box” is a system or component where the inputs, outputs, and general function are known, but the contents of which are not shown. These “black box” representations, hereinafter called “modules,” mask the complexities therein, typically showing only input/output ports.
An IC design can be represented at different levels of abstraction, such as at the register-transfer level (RTL) and at the logic level, using a hardware description language (HDL). VHDL® and Verilog® are examples of HDL languages. At any abstraction level, an IC design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using Boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip-flops.
Set forth above is some very basic information regarding integrated circuits and other circuit schematics that are represented in netlists. Systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, such systems generally operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
While there is extensive testing of designs of electronic devices in the design phase, there is also a need for testing of electronic devices after manufacture to eliminate devices having manufacturing flaws. Currently, memory arrays are tested by adding self-test circuitry which requires many additional gates or by bringing the input and outputs out to the device pins, or by wrapping test circuitry around the memory array.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned and/or other deficiencies and inadequacies.